This invention relates to an amplifier circuit, and in particular to an amplifier which is suitable for use at radio frequencies, and is suitable for integration using CMOS fabrication techniques, with low supply voltages. As such, the device is suitable for use in hand-held portable radio devices, such as mobile phones, for example.
Amplifier circuits, such as those shown in FIG. 1, are known which include a first pair of CMOS transistors 16, 18 in an inverter structure 12, with the inverter output 20 supplied to the amplifier output terminal 22. The input voltage 14, supplied to the inverter input, produces an output current which depends on the transconductances of the transistors 16, 18. The amplifier output terminal is also connected to the gate terminals and to the drain terminals of two further CMOS transistors 24, 26. The output current is drawn through these transistors 24, 26, which act as resistors, in that the current through their drains depends on their gate voltages. The gate voltages, and hence the amplifier output 22, therefore depend on the output current.
As a result, by designing the circuit such that the first pair of transistors are larger than the second pair, an inverting amplifier having a gain greater than unity can be obtained.
FIG. 2 shows a small signal model for such a circuit, in which transistors 24 and 26 have each been represented by their equivalent resistances.
The current iT flowing from the output to the drain of each of the transistors 16, 18 is given by:
iT=gm16xc2x7Vi+gm18xc2x7Vi=Vi(gm16+gm18)
Thus,             V      o        =                                                      -              1                                                      g                                  m                  24                                            +                              g                                  m                  26                                                              -                                    V              i                        ⁡                          (                                                g                                      m                    16                                                  +                                  g                                      m                    18                                                              )                                      ⁢                  
                ∴                  A          v                    =                                    V            o                                V            i                          =                  -                      (                                                            g                                      m                    16                                                  +                                  g                                      m                    18                                                                                                g                                      m                    24                                                  +                                  g                                      m                    26                                                                        )                                ,
where Av is the voltage gain of the circuit.
Normally, the devices are chosen such that gm16=gm18, and gm24=gm26 and set such that gm16=K.gm26 
Thus,                     A        v            =                        -                                    g                              m                16                                                    g                              m                24                                                    =                  -          K                      ⁢          xe2x80x83            where    ,                  g        m            =                        2          ⁢          β          ⁢                      xe2x80x83                    ⁢                      I            D                                ,  
ID Being the current through a device, so       A    v    =                              I                      D            16                                    I                      D            24                                =    K  
The ratio of currents between transistors 16/18 and transistors 24/26 is set to             I              D                  16          /          18                            I              D                  24          /          26                      =      K    2  
For a low-noise amplifier, there are two requirements which are of particular note here. Firstly, it is preferable to match the signal source impedance to the amplifier input impedance, to provide optimum power transfer to the output. Secondly, it is necessary to have a good noise figure, for example of 2 dB or less. However, matching the signal source impedance to the amplifier input impedance produces a noise figure of at least 3 dB, which means that it is not possible to produce an acceptable noise performance.
The present invention provides an amplifier circuit which is suitable for integration using CMOS techniques, and for use at radio frequencies, while providing good performance in terms of its noise figure.
According to a first aspect of the present invention, there is provided an amplifier circuit, comprising:
a circuit input, and a circuit output;
an inverter connected between first and second supply voltages, and having an inverter input connected to the circuit input, and an inverter output, and providing an inverter output current corresponding to a circuit input voltage;
a first resistive element connected to the inverter output and to the circuit output, and providing a voltage output corresponding to the inverter output current; and
a second resistive element providing a feedback resistance between the circuit output and the circuit input, the feedback resistance being adjustable such that the active input impedance of the amplifier can be set to any required value.
According to another aspect of the invention, there is provided an amplifier circuit, comprising:
a circuit input, and a circuit output;
an inverter, comprising first and second MOS transistors (16,18) connected between first and second supply voltages, and having an inverter input connected to the circuit input, and an inverter output, and providing an inverter output current corresponding to a circuit input voltage;
a first resistive element, comprising at least a third MOS transistor (24 or 26), connected to the inverter output and to the circuit output, and providing a voltage output corresponding to the inverter output current; and
a second resistive element, comprising at least a fourth MOS transistor (30 or 32), having its drain and source terminals connected between the circuit output and the circuit input, and having its gate connected to a voltage source to have a voltage applied thereto such that the fourth MOS transistor operates in its linear region.
According to another aspect of the invention, there is provided an amplifier circuit, comprising:
a circuit input, and a circuit output;
an inverter, comprising first and second MOS transistors (16, 18) connected between first and second supply voltages, and having an inverter input connected to the circuit input, and an inverter output, and providing an inverter output current corresponding to a circuit input voltage; and
a resistive element comprising third and fourth MOS transistor (30,32), being of opposite conductivity types, each having its drain source path connected between the circuit output and the circuit input, and having its gate connected to a respective voltage source to have a voltage applied thereto such that it operates in its linear region.
According to another aspect of the invention, there is provided an amplifier circuit, comprising:
a circuit input, and a circuit output;
an inverter, comprising at least a first MOS transistor (16 or 18) connected between the circuit output and a first supply voltage, and having an inverter input connected to the circuit input, and an inverter output, and providing an inverter output current corresponding to a circuit input voltage;
a first resistive element, comprising a second MOS transistor (24 or 26), having its gate and drain connected to the inverter output and to the circuit output, and its source connected to the first supply voltage, providing a voltage output corresponding to the inverter output current;
a second resistive element, comprising third and fourth MOS transistors (30,32), the third and fourth transistors being of opposite conductivity types, and each having its drain-source path connected between the circuit output and the circuit input, and having its gate connected to a respective voltage source; and,
a third resistive element connected between the circuit output and a second supply voltage.